Position:Senior Design Verification Engineer (eInfochips Inc) Job Description: What Youll Be Doing: Testbenches: Build scalable verification environments using UVM and SystemVerilog. Planning: Create detailed verification plans from architectural specifications. Execution: Write, run, and debug constrained-random tests
Grow with us About this opportunity: ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work schedule Your Work Powers the Worlds 5G Networks Not a simulation. Not a demo environment.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture
We are sharing a specialised part-time consulting opportunity for experienced digital chip design and verification professionals with strong backgrounds in RTL development, SystemVerilog, ASIC workflows, verification infrastructure, and frontier silicon engineering workflows. This role supports current
About the Company We are partnering with a globally established, NASDAQ-listed fintech company and a leading provider of commerce enablement, cashless payments, and loyalty solutions. With over 1,200 employees across 13 offices worldwide, the company manages
Commitment: Full-time preferred; high availability required (40 hours) Duration: Target engagement of ~3+ months Location: Remote, USA and Canada only RTL Design Engineer Qualifications 3-10 years of experience in digital RTL design Strong proficiency in Verilog