Position Summary Odyssey Systems has an exciting new opportunity for a Cost Analyst to join our team of analysts developing, updating, and defending Life Cycle Cost Estimates (LCCEs) / Program Office Estimates (POEs) across Radar and
Deadline Date: Wednesday 10 June 2026 Requirement: JChat Engineering Support Location: Offsite with remote access to NCIA software factory and collaborating with NCIA team members with occasional travel to locations throughout NATO Note: Please refer to
Cost Analyst Odyssey Systems has an exciting new opportunity for a Cost Analyst to join our team of analysts developing, updating, and defending Life Cycle Cost Estimates (LCCEs) / Program Office Estimates (POEs) across Radar and
Position Summary Odyssey Systems has an exciting new opportunity for a Cost Analyst to join our team of analysts developing, updating, and defending Life Cycle Cost Estimates (LCCEs) / Program Office Estimates (POEs) across Radar and
We are sharing a specialised part-time consulting opportunity for experienced digital chip design and verification professionals with strong backgrounds in RTL development, SystemVerilog, ASIC workflows, verification infrastructure, and frontier silicon engineering workflows. This role supports current
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam DAngelo, Larry Summers, and Jack Dorsey. Position: RTL
Commitment: Full-time preferred; high availability required (40 hours) Duration: Target engagement of ~3+ months Location: Remote, USA and Canada only RTL Design Engineer Qualifications 3-10 years of experience in digital RTL design Strong proficiency in Verilog