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Step into the role of Digital ASIC Verification Engineer, focusing on innovative chip design from the comfort of your home in the USA or Canada. Leverage your expertise in SystemVerilog and UVM to make a significant
Commitment: Full-time preferred; high availability required (40 hours) Duration: Target engagement of ~3+ months Location: Remote, USA and Canada only RTL Design Engineer Qualifications 3-10 years of experience in digital RTL design Strong proficiency in Verilog
